Learn the most common beginner PCB design mistakes that can negatively impact EMI and SI, as well as how to fix them. Check out tips and tricks on trace widths, clearances, decoupling, vias, and more! Created by Philip Salmony, Tech Consultant for Altium and the mind behind Phil’s Lab.
00:42 #1 Trace Spacing
03:40 #2 Trace Widths
06:01 #3 Via Sizing
08:21 #4 Decoupling
10:46 #5 Reference Planes
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3 times did not start, but then it worked
Wouldn't you want to place the decouppling capacitor closest to the IC and THEN place the VIAs (so your arrangement would look as following: VIA -> capacitor pad -> IC power pin)? Since with your arrangement, in the instant of the IC requirimg more current the direction of flow of current will be capacitor -> VIA -> IC and … -> VIA -> IC pad and after that, when charge will be moved back to the capacitor the direction of flow of current will be … -> VIA -> IC and … -> VIA -> capacitor. This would result in a much bigger change of the electromagnetic field, compared to having a uniform direction of flow of current from the "VIA -> capacitor -> IC"-arrangement.
Edit: please correct me if I'm wrong
Apperently Youtube wants me to watch this video.
Can I ask wjat a PCB is?
Rooting? I think you mean routing.
How DO YOU OPEN A setup ALL OF THE TUTORIALS START WITH A setup
e understand tNice tutorialngs in better depth. I didn't even realize i was just scratcNice tutorialng the surface with tNice tutorials DAW. I'm using soft and soft one and I
Unfortinally at the decoupling section, its wrong to put the vias at the position where you put them! The power should flow over a capacitor into the pin, so the vias MUST be located behind the capacitor and not between capacitor and uC Pin. For several reasons: first and more obvious, is at doing like that, you are decreasing inductance of the trace, and by doing like that current flows only in one direction, and not splitting into 2 ways, and third reason is, by not doing like that you are increasing the electromagnetic radiation.
Excellent! I'm passing this to my students!
Very clear, informative and straightforward, I like to see this guy more often.
Altium. More of this guy. He did great.
cool, can you make a tutorial on how to do that on KiCad?
Very inspiring and thoughtful video, congrats. However, there's something I just don't get it: in 4:10 you've claimed that for high impedance signals one must reduce traces width. I believe you, but there is any chance that you point me out to the theory behind such statement? My first thoughts are on impedance matching fact, however I want to be sure, and if I'm wrong, to understand your claim Thank you in advanced! 😀
The via+cap configuration feels fishy to me and I see others agreeing with my opinion…
Nice to see you here, Phil 🙂
Hi Phil, Glad to see you here.
I'd like to point out 09:55 where you placed vias between MCU and Capacitor.
Robert Feranec discouraged this practice saying the capacitor will have not help much cuz it is out of the way.
He recommended Power trace should pass through the pad of capacitor.
See his video series where he created magic wand Board.
Can you explain what's better to do?
TNice tutorials is exactly about everytNice tutorialng that you'll ever need to do to make soft on soft soft
Despite being an Aussie and using metric my entire life I've used imperial 0.1" scale literally since the first days of Protel. My brain just can't work back to using mm for pcb stuff 🙁
a real design flaw is to put a 48 volt backlight power trace next to the data trace on the ribbon cable to the display where it could arc over and blow the cpu.
on certain macbooks there was a flaw where the 48 volt backlight trace was next to the data trace that goes to the cpu so if the backlight circuit was to arc over it would fry the cpu.
having the decoupling caps close to the power rails makes better security sense if you intend to pot the chip you can include the decoupling caps in the blob of plastic so it would not be so easy for a hacker to glitch the device and dump the firmware.
the apple air tag was hacked because apple placed the decoupling caps far enough away from the chips that someone was able to solder onto the the caps and glitch the device and bypass the built in anti dumping of the firmware.
Why does Altium not use fluid curved tracks which are calculated on the "repellent" formulae that I learned in 1976?
Can we convert smd component to through hole in pcb layout
Heyyyyyyy It's Phil !
For the first rule of thumb, what happens when the board is a 2 layer board and the dielectric thickness is much greater?
Lack of copper balance on inner layers is also one of them. You cant expect to have the same prepreg thickness on a layer with 10% copper as on a layer with 80% on the same PCB. Designers need to learn that good copper balance of at least 80% is king.
The recommendation of vias between bypass cap and device pad is just plain wrong.
When you look at the model of noise conducted trough such an arrangement, this is a poor choice. Always place the bypass cap between the device power pins and the vias to the power layers. There are multiple applications notes that cover this from Linear Technology and similar companies. Also ANY extra trace length between power pins lowers the resonance frequency of noise. Refer to Renesas App note #AN1325 for general overview. My old friend, the late, great Jim Williams, has written several articles and covers some of this in his books. I suggest you read them to better understand the reason why in almost all situations placing the via Between the capacitor and device pins is a really bad idea.
Yep, useful or me as a beginner, thanks man.
We want more content with Phil ! Thank you for the advice!
Thank you Altium team , for every time sharing such technical knowledge. 🙏
I designed a pcb with all the components but I don't think I will ever get an actual PCB because I can't route the traces. It's much harder than I thought when it gets complex. I put 2x 40pin connections and a transistor per pin but I can't get it all routed properly. Oh well, it was fun to make the circuit, it will just never be a product unfortunately.
Shouldn't the vias be on the other side of the capacitor?
Is there a DRC rule to check if trace runs over GND?
Yo phil's here!
Highly recommend checking out his channel ( Phil's Lab ) for more advanced stuff. I learned alot from his videos.
Phil, thanks for pointing out the need to avoid thin annular rings… I presume problems can arise due to drill tolerances?
i'm pretty sure that the last one, at least as demonstrated, should not be even considered to be a mistake, not one little bit. Just the solder joint on the chip the trace goes from is probably an order of magnitude more of a disruption, than the tiny bit of opening of the round plane below a tiny fraction of the length of the track.
PHIL!!!! I'll always recognize his voice…
“routing” should be pronounced “rouww” as in “a family row”. Your pronunciation in Australia means to have sex!
I learnt many things from your video. Thank you !